DESIGN OF A NEW MODIFIED CLOCK GATED SENSE-AMPLIFIER FLIP-FLOP
In this paper a new modified explicit-pulsed clock gated sense-amplifier flip-flop (MCG-SAFF) is proposed for low power and high performance applications. By embedding dual-edge triggering mechanism and conditional pre-charging in the new symmetric latch, the MCG-SAFF is capable to achieve low power dissipation and delay. The simulations are carried out in mentor graphics tools of 130nm technology. From this it is evident that with the proposed design there is 22.1% reduction in power dissipation and 76.5% in delay. When the switching activity is less than 0.5, the proposed MCG- SAFF shown its superiority in terms of power reduction. During zero input switching activity, MCG- SAFF can realize upto 86% in power saving.