摘要：

Scan test is a powerful and popular test technique because it can control and observe the internal states. However, scan path would be used to discover the internals of crypto hardware, which presents a significant security risk of information leakage. An interesting robust secure scan design technique by inserting inverter and XOR gates into the internal scan path to complicate the scan structure has been recently presented. Unfortunately, it still carries the potential of being attacked through differential cryptanalysis of the information scanned out from chips. Therefore, in this paper we propose secure scan architecture, called SSS design. By using the SSS design into the chip, testing and accessing scan chains are guaranteed to be allowed only by an authorized user. The proposed technique has a negligible area overhead, has no negative impact on chip performance and places several levels of security over the scan chain protecting it from potential attacks. The modified scan design makes it more difficult to discover the internal scan architecture.

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